The invention relates to a method for fabricating semiconductor devices, and in particular to a method for forming a titanium nitride layer utilized in the fabrication of DRAM capacitors.
Dynamic Random Access Memory (DRAM) is a widely used integrated circuit. Currently, common DRAM cells comprise a transistor and a capacitor. As is known to those familiar with the art, a capacitor is used to store electric charges, which provide electronic information. The capacitor must contain a sufficiently large capacitance, so that loss of information is avoided and refresh frequency is reduced.
Highly integrated DRAM elements are fulfilled by capacitors having three dimensional structures. In terms of material, capacitors typically comprise metal-insulator-metal (MIM), or a metal-insulator-semiconductor (MIS). Capacitance can be increased by enlarging the surface area of a storage plate, increasing the dielectric constant of the dielectric layer, or reducing thickness of the dielectric layer. In the first method, capacitors with rugged surfaces, such as fin or tree shapes are provided. The third method is disadvantageous as the thickness of the dielectric layer is already very thin, and when thinned to less than 50 angstroms, direct tunneling is easily induced, causing excess leakage. Thus, much research has been directed into dielectric material with high dielectric constant to replace the commonly used silicon oxide. Tantalum pentoxide (Ta2O5) is a result, replacing SiO2 or Si3N4 as a more ideal dielectric material due to its high dielectric constant of, about three times that of Si3N4, i.e. 22˜25. Hence, the stored charges can be greatly increased and element performance is improved.
A typical stacked capacitor structure utilizing Ta2O5 as the dielectric layer is shown in FIG. 1, wherein 2 represents the MOS transistor, 10 represents a plug and lower electrode plate comprising conductive material, such as polysilicon or tungsten, 12 is the Ta2O5 capacitive dielectric layer, 14 is the upper electrode plate formed by TiN, and 16 is the inner dielectric layer. Although not shown in the figure, the capacitive dielectric layer 12 separates the upper electrode plate and the lower electrode plate. The upper electrode plate of TiN on the Ta2O5 capacitive dielectric layer is typically formed by chemical vapor deposition and annealing.
The uniform TiN film serving as the top electrode, however, is not easily formed by conventional CVD methods using TiCl4 and NH3 as precursors. Consequently, leakage is likely to occur at the thin portion of the top electrode if the TiN layer is non-uniform.